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MGM858

R_DATAM

R_DATAP

REF_CLK

SLICE_CTR

R_PWR

R_ENABLE

S_PWR

S_CLK

S_DATA

S_ENABLE

GPP

T_PWR

T_ENABLE

ANT_SW1

ANT_SW0

LEVEL

SHIFTER

AGM

BURST

MODE

LOGIC

(BML)

CLOCK

GENERATOR

(CLG)

TIMING

CONTROL

BLOCK

(TICB)

WATCHDOG

TIMER

(WDT)

ISB

RESET

GENERATOR

(RGE)

DIGITAL

CONTROL

OF

ANALOG

(DCA)

80CL51 CORE

ROM

(64 kBYTES)

AB-MICROCONTROLLER

INTERFACE (ABCIF)

LEVEL SHIFTER

PORT 0

8

8

8

8

LEVEL SHIFTER

PORT 2

LEVEL SHIFTER

PORT 1

LEVEL SHIFTER

PORT 3

AUX-RAM

(3 kBYTES)

MICROCONTROLLER-RAM

(256 BYTES)

UART

SYSTEM

DATA

RAM

(SDR)

(1 kBYTE)

DIGITAL

SIGNAL

PROCESSOR

(DSP)

MEMORY

DIGITAL

DECIMATING

FILTER

(DDF)

DIGITAL

NOISE

SHAPER

(DNS)

DIGITAL

PULSE

SHAPER

(DPS)

DIGITAL

PULSE

SHAPER

(DPS)

LEVEL

SHIFTER

DIGITAL

RECEIVE

FILTER

(DRF)

ANALOG VOLTAGE

REFERENCE

(AVR)

POWER-ON-RESET

(POR)

ANALOG

VOLTAGE

SOURCE

(AVS)

AUXILIARY

ADC

(AAD)

Σ ∆

1-BIT ADC

ATS

1-BIT DAC (ARD)

AMP

Vref

BUZZER BUFFER

(ABB)

CODEC

VDDD

VDDD

VDDD

VDD(BZ)

VDDD

VDDA

VDD(RF)

VDDD

ALE

A16

VDD(OSC)

VDDD

VDD(BAT)

VDDA

T_GSMK/

T_DATA

XTAL1

XTAL2

M_RESET

VBGP

VANLO

MICM/LIFP

MICP/LIFM

EARM

EARP

BZM

BZP

ANALOG SWITCH (ASW)

Vref

ANALOG SUBTRACTOR (ASU)

VDD(BAT)

ANALOG RSSI TREATMENT (ART)

RSSI_AN

ADJUSTABLE CURRENT SOURCE (ACS)

VANLI

VDDD

P0

P2

VDDD

VDD(P0, P2)

VDD(P1, P3)

MICROCONTROLLER

PCD509x2

IB BUS

LEVEL

SHIFTER

EA

PSEN

digital pins

supply pins

analog pins

VSSD

VDD(P1, P3)

VDD(P0, P2)

VSS(P0, P2)

VDD(BZ)

VSS(BZ)

VDD(RF)

VSS(RF)

VDDA

VSSA

VDD(OSC)

VSS(OSC)

VDD(BAT)

LEVEL

SHIFTER

LEVEL

SHIFTER

LEVEL

SHIFTER

LEVEL

SHIFTER

LEVEL

SHIFTER

SPEECH

INTERFACE

IOM® ADPCM

(SPI)

ISB BUS

CONTROLLER

(IBC)

Fig.1 Block diagram.

(1) Ports 1 and 3 are shared with alternative functions.