1997 Feb 13

12

Philips Semiconductors

Product specification

256 to 1024

× 8-bit CMOS EEPROMs with

PCF85xxC-2 family

Note

1. The hold time required (not greater than 300 ns) to bridge the undefined region of the falling edge of SCL must be

internally provided by a transmitter.

SDA input/output (pin 5)

LOW level input voltage

−0.8

V

HIGH level input voltage

+6.5

V

LOW level output voltage

−

0.4

V

output leakage current

−

1

µA

input capacitance

−

7pF

Data retention time

data retention time

−

years

SYMBOL

PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

clock frequency

0

100

kHz

bus free time between a STOP and START

condition

4.7

−µs

START condition hold time after which first clock

pulse is generated

4.0

−µs

LOW level clock period

4.7

−µs

HIGH level clock period

4.0

−µs

set-up time for STARt condition

repeated start

4.7

−µs

data hold time

for bus compatible masters

5

−µs

for bus devices

note 1

0

−

ns

data set-up time

250

−

ns

SDA and SCL rise time

−

1

µs

SDA and SCL fall time

−

300

ns

set-up time for STOP condition

4.0

−µs

SYMBOL

PARAMETER

CONDITIONS

MIN.

MAX.

UNIT