ICS9FG108 datasheet(5/13 Pages) ICST

5 / 13 page

Integrated

Circuit

Systems, Inc.

ICS9FG108

Advance Information

0823—04/02/04

Absolute Max

Symbol

Parameter

Min

Max

Units

VDD_A

3.3V Core Supply Voltage

VDD + 0.5V

VDD_In

3.3V Logic Input Supply Voltage

GND - 0.5

VDD + 0.5V

Storage Temperature

-65

150

°C

Tambient

Ambient Operating Temp

°C

Tcase

Case Temperature

115

°C

ESD prot

Input ESD protection

human body model

2000

Electrical Characteristics - Input/Supply/Common Output Parameters

TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS NOTES

Input High Voltage

VIH

3.3 V +/-5%

VDD + 0.3

Input Low Voltage

VIL

3.3 V +/-5%

VSS - 0.3

0.8

Input High Current

IIH

VIN = VDD

-5

IIL1

VIN = 0 V; Inputs with no pull-

up resistors

-5

IIL2

VIN = 0 V; Inputs with pull-up

resistors

-200

Full Active, CL = Full load;

f = 400 MHz

250

Full Active, CL = Full load;

f = 100 MHz

200

Input Frequency

VDD = 3.3 V

MHz

Pin Inductance

Lpin

7nH

CIN

Logic Inputs

1.5

COUT

Output pin capacitance

Clk Stabilization

1,2

TSTAB

From VDD Power-Up and after

input clock stabilization to 1st

clock

1.8

1,2

Modulation Frequency

fMOD

Triangular Modulation

kHz

DIF output enable

tDIFOE

DIF output enable after

DIF_Stop# de-assertion

Input Rise and Fall times

tR/tF

20% to 80% of VDD

1Guaranteed by design and characterization, not 100% tested in production.

2See timing diagrams for timing requirements.

3 Input frequency should be measured at the REFOUT pin and tuned to ideal 14.31818MHz or 25 MHz to meet

ppm frequency accuracy on PLL outputs.

Input/Output

Capacitance

Input Low Current

IDD3.3OP

Operating Supply Current

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