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LM9628SAMPLE-KIT 데이터시트(PDF) 1 Page - National Semiconductor (TI) |
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LM9628SAMPLE-KIT 데이터시트(HTML) 1 Page - National Semiconductor (TI) |
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1 / 2 page ![]() ©2002 National Semiconductor Corporation www.national.com ADVANCE INFORMATION LM9628 Color CMOS Image Sensor VGA 30 FPS General Description The LM9628 is a high performance, low power, 1/3” VGA CMOS Active Pixel Sensor capable of capturing color digital still or motion images and converting them to a digital data stream. In addition to the active pixel array, an on-chip 12 bit A/D conver- tor, fixed pattern noise elimination circuits, a video gain and sep- arate color gain amplifier are provided. Furthermore, an integrated programmable smart timing and control circuit allows the user maximum flexibility in adjusting integration time, active window size, gain and frame rate. Various control, timing and power modes are also provided. The excellent linear dynamic range of the sensor can be extended to above 100dB by programming a non linear response curve that matches the response of the human eye. Features f Video or snapshot operations f Programmable pixel clock, inter-frame and inter-line delays. f Programmable partial or full frame integration f Programmable gain and individual color gain adjustment f Horizontal & vertical sub-sampling (2:1 & 4:2) f Programmable digital video response curve f Windowing f External snapshot trigger & event synchronisation signals f Auto black level compensation f Flexible digital video read-out supporting programmable: - polarity for synchronisation and pixel clock signals - leading edge adjustment for horizontal synchronization f Programmable via 2 wire I 2C compatible serial interface f Power on reset & power down mode Applications f Dual Mode Camera f Digital Still Camera f Security Cameras f Machine Vision f Automotive Key Specifications Array Format Total: 664H x 504V Active: 648H x 488 V Effective Image Area Total: 4.98 mm x 3.78 mm Active: 4.86 mm x 3.66 mm Optical Format 1/3“ Pixel Size 7.5 µm x 7.5µm Video Outputs 8,10 & 12 Bit Digital Frame Rate 30 frames per second Dynamic Range 62dB in linear mode 110dB in non linear mode Electronic Shutter Rolling reset FPN 0.1% PRMU 1.5% Sensitivity 2.7 V/lux.s Quantum Efficiency 27% Fill Factor 47% Color Mosaic Bayer pattern Package 48 CLCC Single Supply 3.3 V +/-10% Power Consumption 120 mW Operating Temp -40 to 85oC APS Array Vertical Horizontal Master Timer Timing Timing Row Address Gen Clock Gen POR I 2C Compatible Register Bank Row Address Decoder Reset Gen 12 Bit A/D R G B AMP Gain Control mux d[11:0] pclk hsync vsync Serial I/F sda sclk sadr Power Control pdwn snapshot extsync Controller (sequencer) mclk oe reset Overall Chip Block Diagram May 2002 |
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