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978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com

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0 - 21

HMC700LP4 / 700LP4E

v11.0411

8 GHz 16-Bit Fractional-N PLL

Table 14. Reg 07h LKD/CSP Register

Bit

name

Width

Default

Description

[9:0]

wincnt_max

10

250

lock detect window

sets the number of consecutive counts of divided Vco that must land inside the

Lock Detect Window to declare LocK

[10]

lkd_enable

1

1

enables internal lock detect function, note output to Lock Detect Flag on LD_

SDO as per Figure 13 controlled by pfd_LD_opEn, Reg 0Bh PFD register

[11]

lkd_winasym_enable

1

0

asymmetrical window

enables lock detect window to only lag or only lead the

divided reference signal at the PFD, see Figure 9

[12]

lkd_win_asym_up_sel

1

0

1 selects lead window when lkd_winasym_enable=1

0 selects lag window when lkd_winasym_enable=1

[13]

ringosc_oneshot_sel

1

0

1 ring osc based one shot for lock detection mode

0 nominal 20nsec analog one shot for lock detection mode

[16:14]

oneshot_duration

3

0

duration of the ringosc based oneshot pulse in lock detection mode

[18:17]

ringosc_cfg

2

0

Lock Detect ringosc frequency trim

“00” fastest “11” slowest

[19]

ringosc_mode

1

0

force ringosc on

[20]

csp_enable

1

1

cycle slip prevention (cSP) enable

See section PFD Lock Detect for more information about this register.

Table 15. Reg 08h Analog EN Register

Bit

name

Width

Default

Description

[0]

bias_en

1

1

enables main chip bias reference

[1]

cp_en

1

1

charge pump enable

[2]

pfd_en

1

1

pfd enable

[3]

refbuf_en

1

reference path buffer enable. Set to 1 for normal operation.

[4]

vcobuf_en

1

1

vco path rF buffer enable

[5]

gpio_pads_en

1

1

gpio pads enable, Pins D0 and D1

required for use of GPo port or Vco Serial Port

[6]

sdo_pad_en

1

1

LD_SDo pad driver enable (Pin 5)

required for use of Lock Detect, Serial Port read operation

or Vco Serial Port operation

[7]

vcodiv_digclk_en

1

1

vco divider output clk to digital enable

[8]

vcodiv_en

1

1

enable vco divider

[9]

reserved

1

0

[10]

vcodiv_dutycyc_mode

1

0

vcodiv duty cycle mode

stretches the Vco divider output when n>32

[11]

reserved

1

0

Set to 0 for normal operation

[12]

rdiv_ref_to_dig_en

1

1

reference input applied to digital when set to 1, non-divided reference signal is

fed to digital (required for normal operation)

[13]

rdiv_refdiv_to_dig_en

1

1

reference divider applied to digital, when set to 1, divided reference signal is fed

to digital (required for normal operation)

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