MB39C604 datasheet(13/36 Pages) CYPRESS

13 / 36 page

Document Number: 002-08441 Rev.*A

Page 13 of 36

MB39C604

8.4

Power-On Sequence

When the AC line voltage is supplied, VBULK is powered from the AC line through a diode bridge, and the VDD pin is charged from

VBULK through an external source-follower BiasMOS.(Figure 8 red path)

When the VDD pin is charged up and the voltage on the VDD pin (VVDD) rises above the UVLO threshold voltage, an internal Bias

circuit starts operating, and MB39C604 starts the dimming control. After the UVLO is released, this device enables switching and is

operating in a forced switching mode (TON = 1.5 µs, TOFF = 78 µs to 320 µs). When the voltage on the TZE pin reaches the Zero

energy threshold voltage (VTZETH = 0.7V), MB39C604 enters normal operation mode. After the switching begins, the VDD pin is also

charged from Auxiliary Winding through an external diode (DBIAS).(Figure 8 blue path)

Around zero cross points of the AC line voltage VVDD is not supplied from VBULK or Auxiliary Winding. It is necessary to set an

appropriate capacitor of the VDD pin in order to keep VVDD above the UVLO threshold voltage in this period. An external diode (D1)

between BiasMOS and the VDD pin is used to prevent discharge from the VDD pin to VBULK at the zero cross points.

Figure 8. VDD Supply Path at Power-On

Figure 9. Power-On Waveform

VBULK

DRV

VDD

VLED

TZE

VTZETH = 0.7V

Force switching (TON=1.5us/TOFF=78us～320us)

Switching start

UVLO Vth = 13V

Normal switching

MB39C604 데이터시트(PDF) 13 Page - Cypress Semiconductor