MB91F465KB datasheet(29/86 Pages) CYPRESS

29 / 86 page

MB91460K Series

Document Number: 002-04602 Rev. *A

Page 29 of 86

9.3.2

Flash Access Timing Settings in CPU mode

The following tables list all settings for a given maximum Core Frequency (through the setting of CLKB or maximum clock modulation)

for Flash read and write access.

9.3.2.1 Flash Read Timing Settings (Synchronous Read)

9.3.2.2 Flash Write Timing Settings (Synchronous Write)

9.3.3

Address Mapping from CPU to Parallel Programming Mode

The following tables show the calculation from CPU addresses to flash macro addresses which are used in parallel

programming.

9.3.3.1 Address Mapping MB91F465Kx

Note: FA result is without 10:0000h offset for parallel Flash programming . Set offset by keeping FA[20] = 1 as described in section

“Parallel Flash programming mode

”.

Core clock (CLKB)

ATD

ALEH

WEXH

WTC

Remark

to 24 MHz

to 48 MHz

to 80 MHz

to 100 MHz

not available on MB91F465Kx

Core clock (CLKB)

ATD

ALEH

WEXH

WTC

Remark

to 32 MHz

to 48 MHz

to 64 MHz

to 80 MHz

to 100 MHz

not available on MB91F465Kx

CPU Address

(addr)

Condition

Flash

sectors

FA (flash address) Calculation

14:8000h to 14:FFFFh

addr[2]==0

SA4, SA6

(8 Kbyte)

FA := addr - addr%00:4000h + (addr%00:4000h)/2

- (addr/2)%4 + addr%4 - 0D:0000h

14:8000h to 14:FFFFh

addr[2]==1

SA5, SA7

(8 Kbyte)

FA := addr - addr%00:4000h + (addr%00:4000h)/2

- (addr/2)%4 + addr%4 - 0D:0000h

+ 00:2000h

08:0000h to 0F:FFFFh

addr[2]==0

SA12, SA14, SA16, SA18

(64 Kbyte)

FA := addr - addr%02:0000 + (addr%02:0000h)/2

- (addr/2)%4 + addr%4 + 00:0000h

08:0000h to 0F:FFFFh

addr[2]==1

SA13, SA15, SA17, SA19

(64 Kbyte)

FA := addr - addr%02:0000h + (addr%02:0000h)/2

- (addr/2)%4 + addr%4 - 00:0000h

+ 01:0000h

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