ZAMC4100 datasheet(39/155 Pages) IDT

39 / 155 page

ZAMC4100 Datasheet

January 26, 2016

Toggling the WDTCLR bit periodically will clear the WDT as well as both post-scalers which will consequently

avoid the WDT reset event. In order to toggle the WDTCLR bit, the MCU should do the following sequence:

1. Read the WDTCONF register

2. Invert the WDTCLR bit

3. Write back the WDTCONF register

This method requires SPI interface to be functional, which is effectively self-diagnostic. This ensures firmware

within the MCU is operational and free from abnormal behavior.

Once the WDT is configured, the write access to register WDTCONF can be locked with setting bit WDTLCK = 1.

This avoids unintentional WDT reconfiguration or disabling caused by an MCU firmware malfunction. If the WDT

is disabled, the current post-scaler values are automatically cleared.

Figure 3.5 shows an example of the MCU and system reset generation by the WDT. Parameters tMCU_RST and

tSYS_RST are specified in Table 1.17. The duration of the system reset pulse is longer than the MCU reset pulse

because the power-off/on cycle of the MCU regulators is executed.

Important notes:

1. If the WDT is enabled and the bit WDTLCK is set, the MCU cannot disable the WDT until the next

power-on-reset.

2. Once the WDTLCK bit is set, it can be cleared only by a power-on reset.

3. The WDTLCK bit does not lock the write for the WDTCLR bit.

4. If the WDT is enabled, the configuration for the MCU reset and system reset time-out (bits SWDPOS and

MWDPOS of register WDTCONF) cannot be changed.

5. The WDT time-base period of 10ms is calculated for the typical value of the OSCL frequency (see

Table 1.14).

6. If a system reset by WDT is generated, the same flow is executed as in the case of a power-on reset (see

Figure 3.1).

Figure 3.5 WDT Operation

WDTEN

MWDPOS

"000" (MCU reset time-out tMCU_TO = 10ms)

SWDPOS

"10" (System reset time-out tSYS_TO = 4x10ms)

tMCU_TO

MCU_RSTN

(internal pin)

SYS_RSTN

(internal signal)

tMCU_RST

tSYS_RST

tSYS_TO

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