ZLED7025 datasheet(24/26 Pages) IDT

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ZSLS7025 Datasheet

April 20, 2016

ESD Protection

All pins have an ESD protection of

≥ ±3500V according to the Human Body Model (HBM). The ESD test follows the

Human Body Model based on MIL 883-H, Method 3015.8.

Pin Configuration and Package

Figure 6.1

ZSLS7025 Pin Assignments

Table 6.1

Pin Description SOP-8

Pin Name

NO.

Description

VDD

Positive power supply input pin. Internally clamped at 5V (typical).

TOFF

Pin for setting off time. An external resistor, RTOFF, connected to this pin forms an RC discharge path to

generate the constant minimum off time of the Q1 external MOSFET.

ADJ

Enable and input peak current control pin.

This pin is pulled up to 4.5V internally to set VCS_TH =0.24V if ADJ is floating. If VADJ<0.5V, the Q1 external

MOSFET shuts down. If 0.5

≤ V

ADJ ≤ 2.4V, VCS_TH = VADJ/10. If VADJ>2.4V, VCS_TH =0.24V.

GND

Ground.

GATE

Driver’s output for the gate of the Q1 external MOSFET.

Current sense input for the boost, peak-current control loop.

Feedback voltage input pin. Used to regulate the current of the LEDs by keeping VFB=0.3V.

OVP

Overvoltage protection input pin. If the voltage at OVP exceeds the over-voltage input threshold, VOVP_TH, the

GATE output shuts down.

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