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ADE9078ACPZ 데이터시트(PDF) 107 Page - Analog Devices

부품명 ADE9078ACPZ
상세설명  High Performance
PDF  108 Pages
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ADE9078ACPZ 데이터시트(HTML) 107 Page - Analog Devices

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ADE9078
Data Sheet
Rev. 0 | Page 106 of 107
Addr. Name
Bits
Bit Name
Settings Description
Reset
Access
1100 1300:1.
1101 1400:1.
1110 1500:1.
1111 1600:1.
[4:0]
LPLINE
This register determines the time used to detect
peak currents in the low power comparator in
PSM2 operating mode. Note that this register
retains its value in PSM2 and PSM3 operating
modes but is reset to its default value upon
entering PSM0 or PSM1.
0x1F
R/W
0x4B9 PGA_GAIN
[15:14] RESERVED
Reserved.
0x0
R
[13:12] VC_GAIN
PGA gain for Voltage Channel C ADC.
0x0
R/W
00 Gain = 1.
01 Gain = 2.
10 Gain = 4.
11 Gain = 4.
[11:10] VB_GAIN
PGA gain for Voltage Channel B ADC. See
VC_GAIN.
0x0
R/W
[9:8]
VA_GAIN
PGA gain for Voltage Channel A ADC. See
VC_GAIN.
0x0
R/W
[7:6]
IN_GAIN
PGA gain for neutral current channel ADC. See
VC_GAIN.
0x0
R/W
[5:4]
IC_GAIN
PGA gain for Current Channel C ADC. See
VC_GAIN.
0x0
R/W
[3:2]
IB_GAIN
PGA gain for Voltage Channel B ADC. See
VC_GAIN.
0x0
R/W
[1:0]
IA_GAIN
PGA gain for Current Channel A ADC. See
VC_GAIN.
0x0
R/W
0x4BA CHNL_DIS
[15:7]
RESERVED
Reserved.
0x0
R
6
VC_DISADC
Set this bit to one to disable the ADC.
0x0
R/W
5
VB_DISADC
Set this bit to one to disable the ADC.
0x0
R/W
4
VA_DISADC
Set this bit to one to disable the ADC.
0x0
R/W
3
IN_DISADC
Set this bit to one to disable the ADC.
0x0
R/W
2
IC_DISADC
Set this bit to one to disable the ADC.
0x0
R/W
1
IB_DISADC
Set this bit to one to disable the ADC.
0x0
R/W
0
IA_DISADC
Set this bit to one to disable the ADC.
0x0
R/W
0x4E0 VAR_DIS
[15:1]
RESERVED
Reserved.
0x0
R
0
VARDIS
Set this bit to disable the total VAR calculation. This
bit must be set before writing the run bit for
proper operation.
0x0
R/W



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