AD9142ABCPZ datasheet(10/73 Pages) AD

10 / 73 page

Data Sheet

AD9142A

DAC LATENCY SPECIFICATIONS

TMIN to TMAX, AVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFS = 20 mA, FIFO level is set to 4 (half of the FIFO depth), unless

otherwise noted.

Table 3.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

WORD INTERFACE MODE

Fine/coarse modulation, inverse sinc, gain/phase compensation off

2× Interpolation

134

DACCLK cycles

4× Interpolation

244

DACCLK cycles

8× Interpolation

481

DACCLK cycles

BYTE INTERFACE MODE

Fine/coarse modulation, inverse sinc, gain/phase compensation off

2× Interpolation

145

DACCLK cycles

4× Interpolation

271

DACCLK cycles

8× Interpolation

506

DACCLK cycles

INDIVIDUAL FUNCTION BLOCKS

Modulation

Fine

DACCLK cycles

Coarse

DACCLK cycles

Inverse Sinc

DACCLK cycles

Phase Compensation

DACCLK cycles

Gain Compensation

DACCLK cycles

LATENCY VARIATION SPECIFICATIONS

Table 4.

Parameter

Min

Typ

Max

Unit

DAC LATENCY VARIATION1

SYNC Off

DACCLK cycles

SYNC On

DACCLK cycles

DAC latency is defined as the elapsed time from a data sample clocked at the input to the AD9142A until the analog output begins to change.

Rev. A | Page 9 of 72

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