ADP1050ACPZ-R7 datasheet(8/93 Pages) AD

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Data Sheet

ADP1050

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

SERIAL BUS TIMING

See Figure 2

Clock Operating Frequency

100

400

kHz

Glitch Immunity

Bus Free Time

tBUF

1.3

µs

Between stop and start conditions

Start Setup Time

tSU;STA

0.6

µs

Repeated start condition setup time

Start Hold Time

tHD;STA

0.6

µs

Hold time after repeated start condition;

after this period, the first clock is

generated

Stop Setup Time

tSU;STO

0.6

µs

SDA Setup Time

tSU;DAT

100

SDA Hold Time

tHD;DAT

125

For readback

300

For write

SCL Low Timeout

tTIMEOUT

SCL Low Time

tLOW

0.6

µs

SCL High Time

tHIGH

0.6

µs

SCL Low Extended Time

tLOW;SEXT

SCL, SDA Rise Time

300

SCL, SDA Fall Time

300

EEPROM

EEPROM Update Time

Time from the update command to

completion of the EEPROM update

Reliability

Endurance2

10,000

Cycles

TJ = 85°C

1000

Cycles

TJ = 125°C

Data Retention3

Years

TJ = 85°C

Years

TJ = 125°C

CS3 is an alternative output current reading that is calculated by the CS1 reading (representing input current), duty cycle, and the main transformer turns ratio.

Endurance is qualified as per JEDEC Standard 22, Method A117, and is measured at −40°C, +25°C, +85°C, and +125°C.

Retention lifetime equivalent at junction temperature as per JEDEC Standard 22, Method A117.

TIMING DIAGRAM

SCL

SDA

tBUF

tHD;STA

tHD;DAT

tHIGH

tSU;DAT

tHD;STA

tSU;STA

tSU;STO

tLOW

Figure 2. Serial Bus Timing Diagram

Rev. A | Page 7 of 92

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