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ADP7182AUJZ-R7 데이터시트(PDF) 30 Page - Analog Devices

부품명 ADP7182AUJZ-R7
상세설명  Positive or negative enable logic
PDF  31 Pages
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제조업체  AD [Analog Devices]
홈페이지  http://www.analog.com
Logo AD - Analog Devices

ADP7182AUJZ-R7 데이터시트(HTML) 30 Page - Analog Devices

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ADP7182
Data Sheet
Rev. I | Page 30 of 31
OUTLINE DIMENSIONS
1.70
1.60
1.50
0.425
0.350
0.275
TOP VIEW
6
1
4
3
0.35
0.30
0.25
BOTTOM VIEW
PIN 1 INDEX
AREA
SEATING
PLANE
0.60
0.55
0.50
1.10
1.00
0.90
0.20 REF
0.05 MAX
0.02 NOM
0.65 BSC
EXPOSED
PAD
PIN 1
INDICATOR
(R 0.15)
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
0.15 REF
2.10
2.00 SQ
1.90
0.20 MIN
Figure 104. 6-Lead Lead Frame Chip Scale Package [LFCSP]
2.00 mm × 2.00 mm Body and 0.55 Package Height
(CP-6-3)
Dimensions shown in millimeters
8
1
5
4
0.30
0.25
0.20
PIN 1 INDEX
AREA
SEATING
PLANE
0.80
0.75
0.70
1.55
1.45
1.35
1.84
1.74
1.64
0.203 REF
0.05 MAX
0.02 NOM
0.50 BSC
EXPOSED
PAD
3.10
3.00 SQ
2.90
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COPLANARITY
0.08
0.50
0.40
0.30
COMPLIANT
TO JEDEC STANDARDS MO-229-WEED-4
PIN 1
INDICATOR
(R 0.15)
TOP VIEW
BOTTOM VIEW
SIDE VIEW
Figure 105. 8-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body and 0.75 Package Height
(CP-8-13)
Dimensions shown in millimeters



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