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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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LM79 데이터시트(PDF) 27 Page - National Semiconductor (TI) |
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LM79 데이터시트(HTML) 27 Page - National Semiconductor (TI) |
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27 / 31 page  Functional Description (Continued) 13.7 SMI Mask Register 2 — Address 44h Power on default <7:0> = 00h Bit Name Read/ Write Description 0 IN4 Read/Write A one disables the corresponding interrupt status bit for SMI interrupt. 1 -IN5 Read/Write A one disables the corresponding interrupt status bit for SMI interrupt. 2 -IN6 Read/Write A one disables the corresponding interrupt status bit for SMI interrupt. 3 FAN3 Read/Write A one disables the corresponding interrupt status bit for SMI interrupt. 4 Chassis Intrusion Read/Write A one disables the corresponding interrupt status bit for SMI interrupt. 5 FIFO Overflow Read/Write A one disables the corresponding interrupt status bit for SMI interrupt. 6 SMI__IN Read/Write A one disables the corresponding interrupt status bit for SMI interrupt. 7 RESET Enable Read/Write <7> = 1 in SM Mask Register 2 enables the RESET in the Configuration Register. 13.8 NMI Mask Register 1 — Address 45h Power on default <7:0> = 00h Bit Name Read/ Write Description 0 IN0 Read/Write A one disables the corresponding interrupt status bit for NMI/IRQ interrupt. 1 IN1 Read/Write A one disables the corresponding interrupt status bit for NMI/IRQ interrupt. 2 IN2 Read/Write A one disables the corresponding interrupt status bit for NMI/IRQ interrupt. 3 IN3 Read/Write A one disables the corresponding interrupt status bit for NMI/IRQ interrupt. 4 Temperature Read/Write A one disables the corresponding interrupt status bit for NMI/IRQ interrupt. 5 BTI Read/Write A one disables the corresponding interrupt status bit for NMI/IRQ interrupt. 6 FAN1 Read/Write A one disables the corresponding interrupt status bit for NMI/IRQ interrupt. 7 FAN2 Read/Write A one disables the corresponding interrupt status bit for NMI/IRQ interrupt. 13.9 NMI Mask Register 2 — Address 46h Power on <7:0> = 01000000 binary Bit Name Read/ Write Description 0 IN4 Read/Write A one disables the corresponding interrupt status bit for NMI/IRQ interrupt. 1 -IN5 Read/Write A one disables the corresponding interrupt status bit for NMI/IRQ interrupt. 2 -IN6 Read/Write A one disables the corresponding interrupt status bit for NMI/IRQ interrupt. 3 FAN3 Read/Write A one disables the corresponding interrupt status bit for NMI/IRQ interrupt. 4 Chassis Intrusion Read/Write A one disables the corresponding interrupt status bit for NMI/IRQ interrupt. 5 FIFO Overflow Read/Write A one disables the corresponding interrupt status bit for NMI/IRQ interrupt. 6 SMI__IN Read/Write A one disables the corresponding interrupt status bit for NMI/IRQ interrupt. Note: The Power on default is 1 for this bit. 7 Chassis Clear Read/Write A one outputs a minimum 20 ms active low pulse on the Chassis Intrusion pin. The register bit self clears after the pulse has been output. www.national.com 27 |
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