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LM81 데이터시트(PDF) 19 Page - National Semiconductor (TI)

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부품명 LM81
상세설명  Serial Interface ACPI-Compatible Microprocessor System
PDF  32 Pages
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제조업체  NSC [National Semiconductor (TI)]
홈페이지  http://www.national.com
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LM81 데이터시트(HTML) 19 Page - National Semiconductor (TI)

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Functional Description (Continued)
8.2 Temperature Interrupts
INT and T_CRIT_A outputs are provided for temperature in-
terrupt. Temperature interrupts have a normal and an ex-
tended option of operation. Each option has three different
modes of operation: Repetitive Interrupt, One-Time Interrupt
and Comparator.
Normal Repetitive Interrupt Mode is shown in
Figure 11
and operates in the following way: T_CRIT_A is disabled.
Exceeding T
HIGH causes an interrupt that will remain active
indefinitely until reset by reading Interrupt Status Register 1.
Once reset if the temperature remains above the T
HIHYST
setpoint the interrupt will again be activated at the comple-
tion of another conversion cycle. If temperature is less than
or equal to T
HIHYST the interrupt will not be activated.
Normal One-Time Interrupt Mode is shown in
Figure 12
and operates in the following way: T_CRIT_A is disabled.
Exceeding T
HIGH causes an interrupt that will remain active
indefinitely until reset by reading Interrupt Status Register 1.
Another interrupt will not occur until the temperature drops to
less than or equal to T
HIHYST and then exceeds THIGH during
a subsequent conversion. After power up this mode is se-
lected as default.
Normal Comparator Mode is shown in
Figure 13 and oper-
ates in the following way: T_CRIT_A is disabled. Exceeding
T
HIGH causes an interrupt that will remain activated until the
temperature is less than or equal to T
HIGH.TLOW is disabled.
DS100072-16
*Note: Interrupt resets occur only when interrupt Status Register 1 is read.
FIGURE 11. Normal Repetitive Interrupt Response
Diagram
DS100072-17
*Note: Interrupt resets occur only when interrupt Status Register 1 is read.
FIGURE 12. One-Time Interrupt Response Diagram
DS100072-18
*Note: Interrupt resets occur only when interrupt Status Register 1 is read.
FIGURE 13. Normal Comparator Mode
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