Preliminary Technical Data

WM8737L

w

AI Rev 3.0 May 2004

27

REGISTER

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

1:0

FORMAT

10

Audio Data Format Select

11: DSP Mode

10: I

01: Left justified

00: Right justified

3:2

WL

10

Audio Data Word Length

11: 32 bits (see Note)

10: 24 bits

01: 20 bits

00: 16 bits

right, left & I2S modes – ADCLRC

polarity

1 = invert ADCLRC polarity

0 = normal ADCLRC polarity

4

LRP

0

DSP Mode – mode A/B select

1 = MSB is available on 1st BCLK

rising edge after ADCLRC rising edge

(mode B)

0 = MSB is available on 2nd BCLK

rising edge after ADCLRC rising edge

(mode A)

6

MS

0

Master / Slave Mode Control

1: Master Mode

0: Slave Mode

R7 (07h)

Digital Audio

Interface

Format

7

SDODIS

0

ADCDAT serial data pin disable

0: ADCDAT pin enabled

1: ADCDAT pin off (high impedance)

Table 14 Audio Data Format Control

Note: Right Justified mode does not support 32-bit data. If WL=11 in Right justified mode, the actual

word length is 24 bits.

To prevent any communication problems on the Audio Interface, the interface is disabled (ADCDAT

tristated and floating) when the WM8737L starts up. Once the Audio Interface and sample rates have

been programmed, the audio interface can be activated under software control by setting the AI bit

(see “Power Management” section).