WM8776 datasheet(29/55 Pages) WOLFSON

29 / 55 page

Product Preview

WM8776

PP Rev 1.91 June 2004

HPLA/ HPRA[6:0]

ATTENUATION LEVEL

00(hex)

∞dB (mute)

2F(hex)

∞dB (mute)

30(hex)

-73dB

79 (hex)

0dB (default)

7D(hex)

+4dB

7E(hex)

+5dB

7F(hex)

+6dB

Table 13 Headphone Volume Control Attenuation Levels

In addition a zero cross detect circuit is provided for the output PGA volume under the control

of bit 7 (ZCEN) in the each attenuation register. When ZCEN is set the attenuation values

are only updated when the input signal to the gain stage is close to the analogue ground

level. This minimises audible clicks and ‘zipper’ noise as the gain values change. A timeout

clock is also provided which will generate an update after a minimum of 131072 master

clocks (= ~10.5ms with a master clock of 12.288MHz). The timeout clock may be disabled by

setting TOD.

BIT

LABEL

DEFAULT

DESCRIPTION

R7 (07h)

0000111

Timeout Clock Disable

TOD

DAC and ADC Analogue Zero

cross detect timeout disable

0 : Timeout enabled

1: Timeout disabled

DAC DIGITAL VOLUME CONTROL

The DAC volume may also be adjusted in the digital domain using independent digital

attenuation control registers

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

7:0

LDA[7:0]

11111111

(0dB)

Digital Attenuation data for Left channel DACL in 0.5dB steps. See

Table 14

R3 (03h)

0000011

Digital

Attenuation

DACL

UPDATED

Not latched

Controls simultaneous update of Attenuation Latches

0: Store LDA in intermediate latch (no change to output)

1: Store LDA and update attenuation on both channels

7:0

RDA[6:0]

11111111

(0dB)

Digital Attenuation data for Right channel DACR in 0.5dB steps. See

Table 14

R4 (04h)

0000100

Digital

Attenuation

DACR

UPDATED

Not latched

Controls simultaneous update of Attenuation Latches

0: Store RDA in intermediate latch (no change to output)

1: Store RDA and update attenuation on both channels.

7:0

MASTDA[7:0]

11111111

(0dB)

Digital Attenuation data for DAC channels in 0.5dB steps. See Table

R5 (05h)

0000101

Master

Digital

Attenuation

(both channels)

UPDATED

Not latched

Controls simultaneous update of Attenuation Latches

0: Store gain in intermediate latch (no change to output)

1: Store gain and update attenuation on channels.

WM8776 데이터시트(PDF) 29 Page - Wolfson Microelectronics plc

WM8776 데이터시트(HTML) 29 Page - Wolfson Microelectronics plc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55

데이터시트 다운로드

링크 URL