WM8753LEBSLASHRV datasheet(30/87 Pages) WOLFSON

30 / 87 page

Advanced Information

WM8753L

AI Rev 3.1 June 2004

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

6:5

ADCPOL

[1:0]

00 = Polarity not inverted

01 = L polarity invert

10 = R polarity invert

11 = L and R polarity invert

VXFILT

ADC Filter Select

0 = HiFi Filter

1 = Voice FIlter

3:2

HPMODE

ADC

High

pass

Filter

Cut-off

Select

00 = 3.4Hz @ fs = 48kHz

01 = 82Hz @ fs = 16kHz

(41Hz @ fs = 8kHz)

10 = 82Hz @ fs = 8kHz

(164Hz @ fs = 16kHz)

11 = 170Hz @ fs = 8kHz

(340Hz @ fs = 16kHz)

HPOR

Store dc offset

1 = store offset

0 = clear offset

R2 (02h)

ADC Control

ADCHPD

ADC High Pass

Filter

Enable

(Digital)

1 = Disable High Pass Filter

0 = Enable High Pass Filter

Table 18 ADC Signal Path Control

DIGITAL ADC VOLUME CONTROL

The output of the ADCs can be digitally amplified or attenuated over a range from –97dB to +30dB in

0.5dB steps. The volume of each channel can be controlled separately. The gain for a given eight-bit

code X is given by:

0.5

× (X-195) dB for 1 ≤ X ≤ 255;

MUTE for X = 0

The LAVU and RAVU control bits control the loading of digital volume control data. When LAVU or

RAVU are set to 0, the LADCVOL or RADCVOL control data will be loaded into the respective control

updated when either LAVU or RAVU are set to 1. This makes it possible to update the gain of both

channels simultaneously.

WM8753LEB/RV 데이터시트(PDF) 30 Page - Wolfson Microelectronics plc

WM8753LEB/RV 데이터시트(HTML) 30 Page - Wolfson Microelectronics plc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87

데이터시트 다운로드

링크 URL