전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

X9521 데이터시트(PDF) 19 Page - Xicor Inc.

부품명 X9521
상세설명  Dual DCP, EEPROM Memory
PDF  26 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  XICOR [Xicor Inc.]
홈페이지  http://www.xicor.com
Logo XICOR - Xicor Inc.

X9521 데이터시트(HTML) 19 Page - Xicor Inc.

Back Button X9521 Datasheet HTML 15Page - Xicor Inc. X9521 Datasheet HTML 16Page - Xicor Inc. X9521 Datasheet HTML 17Page - Xicor Inc. X9521 Datasheet HTML 18Page - Xicor Inc. X9521 Datasheet HTML 19Page - Xicor Inc. X9521 Datasheet HTML 20Page - Xicor Inc. X9521 Datasheet HTML 21Page - Xicor Inc. X9521 Datasheet HTML 22Page - Xicor Inc. X9521 Datasheet HTML 23Page - Xicor Inc. Next Button
Zoom Inzoom in Zoom Outzoom out
 19 / 26 page
background image
REV 1.1.9 1/30/03
Characteristics subject to change without notice.
19 of 26
www.xicor.com
X9521
– Preliminary Information
A.C. CHARACTERISTICS (See Figure 22, Figure 23, Figure 24)
A.C. TEST CONDITIONS
NONVOLATILE WRITE CYCLE TIMING
CAPACITANCE (TA = 25˚C, F = 1.0 MHZ, VCC = 5V)
Notes: 1.
Typical values are for TA = 25˚C and VCC = 5.0V
Notes: 2.
Cb = total capacitance of one bus line in pF.
Notes: 3.
Over recommended operating conditions, unless otherwise specified
Notes: 4.
tWC is the time from a valid STOP condition at the end of a write sequence to the end of the self-timed internal nonvolatile write
cycle. It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
Notes: 5.
This parameter is not 100% tested.
Symbol
Parameter
400kHz
Min
Max
Units
fSCL
SCL Clock Frequency
0
400
KHz
tIN (5)
Pulse width Suppression Time at inputs
50
ns
tAA (5)
SCL LOW to SDA Data Out Valid
0.1
0.9
µs
tBUF (5)
Time the bus free before start of new transmission
1.3
µs
tLOW
Clock LOW Time
1.3
µs
tHIGH
Clock HIGH Time
0.6
µs
tSU:STA
Start Condition Setup Time
0.6
µs
tHD:STA
Start Condition Hold Time
0.6
µs
tSU:DAT
Data In Setup Time
100
ns
tHD:DAT
Data In Hold Time
0
µs
tSU:STO
Stop Condition Setup Time
0.6
µs
tDH (5)
Data Output Hold Time
50
ns
tR (5)
SDA and SCL Rise Time
20 +.1Cb
(2)
300
ns
tF (5)
SDA and SCL Fall Time
20 +.1Cb
(2)
300
ns
tSU:WP
WP Setup Time
0.6
µs
tHD:WP
WP Hold Time
0
µs
Cb
Capacitive load for each bus line
400
pF
Input Pulse Levels
0.1VCC to 0.9VCC
Input Rise and Fall Times
10ns
Input and Output Timing Levels
0.5VCC
Output Load
See Figure 20
Symbol
Parameter
Min.
Typ.(1)
Max.
Units
tWC(4)
Nonvolatile Write Cycle Time
5
10
ms
Symbol
Parameter
Max
Units
Test Conditions
COUT (5)
Output Capacitance (SDA, V1RO, V2RO, V3RO)
8
pF
VOUT = 0V
CIN (5)
Input Capacitance (SCL, WP)
6
pF
VIN = 0V



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26


데이터시트 다운로드

Go To PDF Page


링크 URL



ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크 투 데이터시트    |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com