ADA4853-1/ADA4853-2/ADA4853-3

Data Sheet

Rev. G | Page 18 of 20

OUTLINE DIMENSIONS

1.30 BSC

COMPLIANT TO JEDEC STANDARDS MO-203-AB

1.00

0.90

0.70

0.46

0.36

0.26

2.20

2.00

1.80

2.40

2.10

1.80

1.35

1.25

1.15

0.10 MAX

1.10

0.80

0.40

0.10

0.22

0.08

3

12

4

6

5

0.65 BSC

COPLANARITY

0.10

SEATING

PLANE

0.30

0.15

Figure 52. 6-Lead Thin Shrink Small Outline Transistor Package [SC70]

(KS-6)

Dimensions shown in millimeters

COMPLIANT TO JEDEC STANDARDS MO-153-AB-1

8°

0°

4.50

4.40

4.30

14

8

7

1

6.40

BSC

PIN 1

5.10

5.00

4.90

0.65 BSC

0.15

0.05

0.30

0.19

1.20

MAX

1.05

1.00

0.80

0.20

0.09

0.75

0.60

0.45

COPLANARITY

0.10

SEATING

PLANE

Figure 53. 14-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-14)

Dimensions shown in millimeters