www.icst.com/products/hiperclocks.html

Aug 02, 2002

1

Integrated

Circuit

Systems, Inc.

HiPerClockS™ Application Note

This application note provides termination examples for HiPerClockS

3.3V LVPECL driver is an open source/emitter driver as shown in Figure 1. Proper termination is required to

ensure proper function of the device and signal integrity. There are many different termination schemes for the

LVPECL drivers. This application note includes standard direct termination and AC coupled termination. The

following termination approaches are only general recommendations under ideal conditions. Board designers

should consult with their signal integrity engineers or verify through simulations in their system environment. The

trace length and physical location of the components can affect signal integrity. The 50-Ohm transmission lines

in the following diagrams indicate whether the components should be located near the driver or near the

receiver.

P.C. Board

VCCO

VCCO

Zo = 50

Q

VCCO-2V

R1

VEE

R3

50

nQ

Zo = 50

R4

50

LVPECL Driver

R2

Figure 1 HiPerClockS

Direct LVPECL Termination

The standard 3.3V LVPECL termination is shown in Figure 2. This termination scheme is used in

characterization. The draw back of using this termination scheme in real applications is that it requires an

additional power supply V

are commonly used. These termination approaches eliminate the need of 1.3V power supply. In Figure 5, R1

and R2 located near the driver serve as current paths for the LVPECL outputs. The R3=100 Ohm located near

the receiving serves as matched load termination for the transmission lines.