AD7477AARM datasheet(17/24 Pages) AD

17 / 24 page

REV. C

AD7476A/AD7477A/AD7478A

–17–

SCLK frequency one dummy cycle is sufficient to power up the

device and acquire VIN, it does not necessarily mean that a full

dummy cycle of 16 SCLKs must always elapse to power up the

device and acquire VIN fully; 1

µs will be sufficient to power up

the device and acquire the input signal. If, for example, a

5 MHz SCLK frequency was applied to the ADC, the cycle

time would be 3.2

µs. In one dummy cycle, 3.2 µs, the part

would be powered up and VIN acquired fully. However, after 1

µs

with a 5 MHz SCLK, only five SCLK cycles would have elapsed.

At this stage, the ADC would be fully powered up and the sig-

nal acquired. In this case, the

CS can be brought high after the

10th SCLK falling edge and brought low again after a time,

tQUIET, to initiate the conversion.

When power supplies are first applied to the AD7476A/AD7477A/

AD7478A, the ADC may power up in either the power-down or

normal mode. Because of this, it is best to allow a dummy cycle

to elapse to ensure that the part is fully powered up before attempt-

ing a valid conversion. Likewise, if it is intended to keep the part

in the power-down mode while not in use and the user wishes

the part to power up in power-down mode, the dummy cycle

may be used to ensure that the device is in power-down by

executing a cycle such as that shown in Figure 10. Once supplies

are applied to the AD7476A/AD7477A/AD7478A, the power-up

time is the same as that when powering up from the power-

down mode. It takes approximately 1

µs to power up fully if the

part powers up in normal mode. It is not necessary to wait 1

µs

before executing a dummy cycle to ensure the desired mode of

operation. Instead, the dummy cycle can occur directly after

power is supplied to the ADC. If the first valid conversion is

performed directly after the dummy conversion, care must be

taken to ensure that an adequate acquisition time has been

allowed. As mentioned earlier, when powering up from the

power-down mode, the part will return to track upon the first

SCLK edge applied after the falling edge of

CS. However,

when the ADC powers up initially after supplies are applied,

the track-and-hold will already be in track. This means, assum-

ing one has the facility to monitor the ADC supply current, if

the ADC powers up in the desired mode of operation and thus

a dummy cycle is not required to change the mode, a dummy

cycle is not required to place the track-and-hold into track.

POWER VS. THROUGHPUT RATE

By using the power-down mode on the AD7476A/AD7477A/

AD7478A when not converting, the average power consumption

of the ADC decreases at lower throughput rates. Figure 12 shows

how as the throughput rate is reduced, the device remains in its

power-down state longer and the average power consumption over

time drops accordingly.

For example, if the AD7476A/AD7477A/AD7478A are oper-

ated in a continuous sampling mode with a throughput rate of

100 kSPS and an SCLK of 20 MHz (VDD = 5 V) and the devices

are placed in the power-down mode between conversions, the

power consumption is calculated as follows. The power dissipation

during normal operation is 17.5 mW (VDD = 5 V). If the power-up

time is one dummy cycle, i.e., 1

µs, and the remaining conversion

VALID DATA

SDATA

SCLK

110

1416

AD7476A/AD7477A/AD7478A

Figure 9. Normal Mode Operation

THREE-STATE

SDATA

SCLK

110

1416

Figure 10. Entering Power-Down Mode

INVALID DATA

SDATA

SCLK

110

116

VALID DATA

THE PART IS FULLY

POWERED UP WITH

VIN FULLY ACQUIRED

THE PART

BEGINS TO

POWER UP

Figure 11. Exiting Power-Down Mode

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