SM588

× series

NIPPON PRECISION CIRCUITS—13

Audio Data Input

Input data format (DATA)

The input data has a format that varies with device within the series, as shown below.

Input timing

3-wire input (DATA, LRCI, BCKI)

Serial data bits on DATA are read into the SIPO register (serial-to-parallel converter register) on the rising

edge of the bit clock BCKI, and then converted to parallel data.

The arithmetic operation and output timing are independent of the input timing. Accordingly, after a reset, as

long as the clock frequency ratio between LRCI and the system clock CLK is maintained, phase differences

between LRCI, BCKI and the system clock CLK do not affect the functional operation. Also, any jitter present

on the data input clock does not appear as output pulse jitter.

2-wire input (DATA, LRCI)

Serial data bits on DATA are read into the SIPO register (serial-to-parallel converter register) on the rising

edge of an internally generated bit clock, and then converted to parallel data.

Deemphasis Filter (DEEM: 2-wire input)

The 2-wire type with built-in digital deemphasis filter is designed to operate at 44.1 kHz. Deemphasis is ON

when DEEM is HIGH, and OFF when DEEM is LOW.

Table 2. Input format

Device

Input length

Format

1.

The 2-wire type supports bit clocks of 48fs (384fs) or 64fs (256fs/512fs) only.

16 bits

MSB first, bit serial, rear-packed,

2s complement

2.

The 3-wire type supports bit clocks of up to 64fs.

24 bits