STK14CA8

December 2004

Document Control #ML0022 rev 1.0

7

MODE SELECTION

E

W

G

MODE

I/O

POWER

NOTES

H

X

X

X

Not Selected

Output High Z

Standby

L

H

L

X

Read SRAM

Output Data

Active

L

L

X

X

Write SRAM

Input Data

Active

L

H

L

0x4E38

0xB1C7

0x83E0

0x7C1F

0x703F

0x8B45

Read SRAM

Read SRAM

Read SRAM

Read SRAM

Read SRAM

Autostore Disable

Output Data

Output Data

Output Data

Output Data

Output Data

Output Data

Active

i

, j, k

L

H

L

0x4E38

0xB1C7

0x83E0

0x7C1F

0x703F

0x4B46

Read SRAM

Read SRAM

Read SRAM

Read SRAM

Read SRAM

Autostore Enable

Output Data

Output Data

Output Data

Output Data

Output Data

Output Data

Active

i

, j, k

L

H

L

0x4E38

0xB1C7

0x83E0

0x7C1F

0x703F

0x8FC0

Read SRAM

Read SRAM

Read SRAM

Read SRAM

Read SRAM

Nonvolatile Store

Output Data

Output Data

Output Data

Output Data

Output Data

Output High Z

Active

ICC2

i

, j, k

L

H

L

0x4E38

0xB1C7

0x83E0

0x7C1F

0x703F

0x4C63

Read SRAM

Read SRAM

Read SRAM

Read SRAM

Read SRAM

Nonvolatile Recall

Output Data

Output Data

Output Data

Output Data

Output Data

Output High Z

Active

i

, j, k

Notes

i: The six consecutive addresses must be in the order listed. W

must be high during all six consecutive cycles to enable a nonvolatile cycle.

j: While there are 17 addresses on the STK14CA8, only the lower 16 are used to control software modes

k: I/O state depends on the state of G . The I/O table shown assumes G

low.