IR2136(2)(3)(5)(6)(7)(8)(J&S)&(PbF)

2

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Recommended Operating Conditions

The Input/Output logic timing diagram is shown in figure 1. For proper operation the device should be used within the recom-

mended conditions. All voltage parameters are absolute referenced to COM. The VS offset rating is tested with all supplies

biased at 15V differential.

High side floating supply voltage

IR2136(8)

IR21362

IR2136(3)(5)(6)(7)

High side floating supply offset voltage

Note 1

600

High side output voltage

Low side output voltage

0

Low side and logic fixed supply voltage

IR2136(8)

10

20

IR21362

11.5

20

IR2136(3)(5)(6)(7)

12

20

Logic ground

-5

5

FAULT output voltage

RCIN input voltage

Symbol

Definition

Min.

Max.

Units

V

(Please refer to the Design Tip DT97-3 for more details).

Note 2: All input pins and the ITRIP pin are internally clamped with a 5.2V zener diode.

Symbol

Definition

Min.

Max.

Units

High side offset voltage

High side floating supply voltage

-0.3

625

High side floating output voltage

Low side and logic fixed supply voltage

-0.3

25

Logic ground

Low side output voltage

-0.3

Input voltage LIN,HIN,ITRIP, EN, RCIN

lower of

FAULT output voltage

dV/dt

Allowable offset voltage slew rate

—

50

V/ns

(28 lead PDIP)

—

1.5

(28 lead SOIC)

—

1.6

( 44leadPLCC)

—

2.0

Thermal resistance, junction to ambient

(28 lead PDIP)

—

83

(28 lead SOIC)

—

78

(44 lead PLCC)

—

63

Junction temperature

—

150

Storage temperature

-55

150

Lead temperature (soldering, 10 seconds)

—

300

V

°C/W

Absolute Maximum Ratings

Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters

are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured under board

mounted and still air conditions.

W

°C