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WM8214

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PP Rev 1.6 March 2004

19

OUTPUT FORMATS

The output from the WM8214 can be presented in several different formats under control of the

OPFORM[1:0] register bits as shown in Figure 14.

MCLK

OP[7:4]

t

PD

AB

C

D

AB

C

D

OP[7:0]

ABABABAB

OP[7:0]

AAA

A

8-bit multiplexed

8-bit parallel

4-bit multiplexed (LEGACY=1)

OP[7:0]

8-bit multiplexed (LEGACY=1)

t

PD

ABA

B

OP[7:0]

8-bit parallel (LEGACY=1)

AA

Figure 14 Output Data Formats

OUTPUT

FORMAT

OPFORM[1:0]

LEGACY

OUTPUT

PINS

OUTPUT

8+8-bit

multiplexed

00, 10

X

OP[7:0]

A = d15, d14, d13, d12, d11, d10, d9, d8

B = d7, d6, d5, d4, d3, d2, d1,d0

8-bit parallel

01

X

OP[7:0]

A = d15, d14, d13, d12, d11, d10, d9, d8

4+4+4+4-bit

(nibble)

11

1

OP[7:4]

A = d15, d14, d13, d12

B = d11, d10, d9, d8

C = d7, d6, d5, d4

D = d3, d2, d1, d0

Table 2 Details of Output Data Formats (as shown in Figure 14).

REFERENCES

The ADC reference voltages are derived from an internal bandgap reference, and buffered to pins

VRT and VRB, where they must be decoupled to ground. Pin VRX is driven by a similar buffer, and

also requires decoupling. The output buffer from the RLCDAC also requires decoupling at pin

VRLC/VBIAS.

POWER MANAGEMENT

Power management for the device is performed via the Control Interface. By default the device is

fully enabled. The EN bit allows the device to be fully powered down when set low. Individual blocks

can be powered down using the bits in Setup Register 5. When in MONO or TWOCHAN mode the

unused input channels are automatically disabled to reduce power consumption.