WM8772 datasheet(53/70 Pages) WOLFSON

53 / 70 page

Production Data

WM8772EFT – 32 PIN TQFP

PD Rev 4.1 October 2004

ADCLRC

ADCBCLK

DOUT

Input Word Length (IWL)

1/fs

LEFT CHANNEL

n-1

LSB

MSB

n-1

RIGHT CHANNEL

NO VALID DATA

1 BCLK

Figure 47 DSP Early Mode Timing Diagram – ADC Data Output

DSP LATE MODE

In DSP late mode, the MSB of DAC channel 1 left data is sampled by the WM8772EFT on the first

DACBCLK rising edge following a DACLRC rising edge. DAC channel 1 right and DAC channels 2

and 3 data follow DAC channel 1 left data (Figure 48).

DACLRC

DACBCLK

DIN1

Input Word Length (IWL)

1/fs

CHANNEL 1

LEFT

n-1

LSB

MSB

n-1

CHANNEL 1

RIGHT

CHANNEL 2

LEFT

n-1

CHANNEL 3

RIGHT

NO VALID DATA

Figure 48 DSP Late Mode Timing Diagram – DAC Data Input

The MSB of the left channel ADC data is output on DOUT and changes on the same falling edge of

ADCBCLK as the low to high ADCLRC transition and may be sampled on the rising edge of

ADCBCLK. The right channel ADC data is contiguous with the left channel data (Figure 49).

ADCLRC

BCK

DOUT

Input Word Length (IWL)

1/fs

LEFT CHANNEL

n-1

LSB

MSB

n-1

RIGHT CHANNEL

NO VALID DATA

Figure 49 DSP Late Mode Timing Diagram – ADC Data Output

In both early and late DSP modes, DACL1 is always sent first, followed immediately by DACR1 and

the data words for the other 6 channels. No BCLK edges are allowed between the data words. The

word order is DAC1 left, DAC1 right, DAC2 left, DAC2 right, DAC3 left, DAC3 right.

WM8772 데이터시트(PDF) 53 Page - Wolfson Microelectronics plc

WM8772 데이터시트(HTML) 53 Page - Wolfson Microelectronics plc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70

데이터시트 다운로드

링크 URL