ASAHI KASEI

[AK5352]

0155-E-00

1997/1

- 4 -

21

SDATA

O

Serial Data Output pin

Data are output with MSB first, in 2's complement format.

After 20 bits are output it turns to "L". It also remains "L" at a

power-down mode(PD="L").

22

CMODE

I

Master Clock Selection pin

"L": MCLK=256fs

"H": MCLK=384fs

23

15

SMODE1

SMODE2

I

I

Serial Interface Mode Select pin

Defines the directions of LRCK, SCLK and FSYNC pins and

Output Data Format. SMODE2 is pull-down pin.

SMODE1 SMODE2

MODE

LRCK

L

L

Slave mode: MSB justified

: H/L

H

L

Master mode: Similar to I

: H/L

L

H

Slave mode: I

: L/H

H

H

Master mode: I

: L/H

24

VB

-

Substrate Power Supply, +5V