AND8090/D

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13

Negative Setup and Positive Hold Example – The

MC100E445 4−Bit Serial/Parallel Converter data sheet

specifies the following:

that the left edge of the timing window is 200 ps after

the active rising clock edge.

that the right edge of the timing window is 300 ps after

the active rising clock edge.

The setup time requirement and the hold time requirement

were both met in the example shown in Figure 33, therefore

the LOW−to−HIGH output transition occurs after the CLK

rising edge propagation delay of 1800 ps. Note that the input

cannot change within the timing window of 100 ps. Only

one of the differential clocks and differential inputs is shown

in Figure 33.

Positive Setup and Negative Hold Example – The

MC100E136 6−Bit Universal Up/Down Counter data sheet

specifies the following:

that the left edge of the timing window is 400 ps before

the active rising clock edge.

that the right edge of the timing window is 250 ps

before the active rising clock edge.

The setup time requirement and the hold time requirement

were both met in the example shown in Figure 34, therefore

the LOW−to−HIGH output transition occurs after the CLK

rising edge propagation delay of 1150 ps. Note that the input

cannot change within the timing window of 150 ps.

Figure 33. Negative Setup and Positive Hold Example

CLK

50%

50% 50%

INPUT

OUTPUT

1800 ps

−200

+300

50%

Figure 34. Positive Setup and Negative Hold Example

CLK

50%

50%

50%

INPUT

OUTPUT

1150 ps

+400

−250

50%