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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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CD74AC74 데이터시트(PDF) 4 Page - Texas Instruments |
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CD74AC74 데이터시트(HTML) 4 Page - Texas Instruments |
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4 / 6 page  CD54AC74, CD74AC74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET SCHS231D – SEPTEMBER 1998 – REVISED DECEMBER 2002 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 timing requirements over recommended operating free-air temperature range, VCC = 1.5 V (unless otherwise noted) –55 °C to 125 °C –40 °C to 85 °C UNIT MIN MAX MIN MAX fclock Clock frequency 9 10 MHz t Pulse duration PRE or CLR low 50 44 ns tw Pulse duration CLK 56 49 ns t Setup time Data 44 39 ns tsu Setup time PRE or CLR inactive ns th Hold time Data after CLK ↑ 0 0 ns trec Recovery time, before CLK ↑ CLR ↑ or PRE↑ 34 30 ns timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) –55 °C to 125 °C –40 °C to 85 °C UNIT MIN MAX MIN MAX fclock Clock frequency 79 90 MHz t Pulse duration PRE or CLR low 5.6 4.9 ns tw Pulse duration CLK 6.3 5.5 ns t Setup time Data 4.9 4.3 ns tsu Setup time PRE or CLR inactive ns th Hold time Data after CLK ↑ 0 0 ns trec Recovery time, before CLK ↑ CLR ↑ or PRE↑ 4.7 4.1 ns timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) –55 °C to 125 °C –40 °C to 85 °C UNIT MIN MAX MIN MAX fclock Clock frequency 110 125 MHz t Pulse duration PRE or CLR low 4 3.5 ns tw Pulse duration CLK 4.5 3.9 ns t Setup time Data 3.5 3.1 ns tsu Setup time PRE or CLR inactive ns th Hold time Data after CLK ↑ 0 0 ns trec Recovery time, before CLK ↑ CLR ↑ or PRE↑ 2.7 2.4 ns |
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