| 전자부품 데이터시트 검색엔진 |
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FDC37C93XAPM 데이터시트(PDF) 94 Page - SMSC Corporation |
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FDC37C93XAPM 데이터시트(HTML) 94 Page - SMSC Corporation |
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94 / 280 page ![]() 94 Table 37 - EPP Pin Descriptions EPP SIGNAL EPP NAME TYPE EPP DESCRIPTION nWRITE nWrite O This signal is active low. It denotes a write operation. PD<0:7> Address/Data I/O Bi-directional EPP byte wide address and data bus. INTR Interrupt I This signal is active high and positive edge triggered. (Pass through with no inversion, Same as SPP.) WAIT nWait I This signal is active low. It is driven inactive as a positive acknowledgement from the device that the transfer of data is completed. It is driven active as an indication that the device is ready for the next transfer. DATASTB nData Strobe O This signal is active low. It is used to denote data read or write operation. RESET nReset O This signal is active low. When driven active, the EPP device is reset to its initial operational mode. ADDRSTB nAddress Strobe O This signal is active low. It is used to denote address read or write operation. PE Paper End I Same as SPP mode. SLCT Printer Selected Status I Same as SPP mode. nERR Error I Same as SPP mode. PDIR Parallel Port Direction O This output shows the direction of the data transfer on the parallel port bus. A low means an output/write condition and a high means an input/read condition. This signal is normally a low (output/write) unless PCD of the control register is set or if an EPP read cycle is in progress. Note 1: SPP and EPP can use one common register. Note 2: nWrite is the only EPP output that can be over-ridden by SPP control port during an EPP cycle. For correct EPP read cycles, PCD is required to be a low. |
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