ACPL-339J datasheet(21/23 Pages) AVAGO

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Dead Time and Propagation Delay Specifications

The ACPL-339J includes a Propagation Delay Difference

(PDD) specification intended to help designers minimize

“dead time” in their power inverter designs. Dead time

is the time period during which both the high and low

side power transistors (Q1 and Q2 in Figure 37) are off.

Any overlap in Q1 and Q2 conduction will result in large

currents flowing through the power devices between the

high and low voltage motor rails.

Figure 36. Minimum LED skew for zero dead time

tPLHMAX

tPHLMIN

Q1 IGBT OFF

Q1 IGBT ON

VOUTP1

VOUTN1

VG(IGBT)Q1

LED1 IF1

tPHLMIN

VOUTP2

VOUTN2

tPLHMAX

tPHLMIN

Q2 IGBT OFF

Q2 IGBT ON

PDD

= tPLHMAX - tPHLMIN

PDD

= tPLHMAX - tPHLMIN

VG(IGBT)Q2

LED2 IF2

To minimize dead time in a given design, the turn on of

LED2 should be delayed (relative to the turn off of LED1)

so that under worst-case conditions, transistor Q1 has

just turned off when transistor Q2 turns on, as shown in

Figure 36. The amount of delay necessary to achieve this

condition is equal to the maximum value of the propa-

gation delay difference specification, PDDMAX, which is

specified to be 200 ns over the operating temperature

range of -40° C to 105° C.

ACPL-339J 데이터시트(PDF) 21 Page - AVAGO TECHNOLOGIES LIMITED