The reference oscillator input block is powered down when both Main_PWDN and Aux_PWDN bits are asserted. The OSC

reverts to a high impedance state when this condition exists. Power down forces the respective charge pump and phase com-

parator logic to a TRI-STATE condition. During the power down condition, both N- and R-counters are held at reset. Upon pow-

ering up, the N-counter resumes counting in “close” alignment with the R-counter. The maximum error is at most one prescaler

cycle. The MICROWIRE interface remains active and it is capable of loading and latching in data during all of the power down

modes.

2.0 Programming Description

2.1 MICROWIRE INTERFACE

The LMX237X register set can be accessed through the MICROWIRE interface. A 22-bit shift register is used as a temporary reg-

ister to indirectly program the on-chip registers. The shift register consists of a 20-bit DATA[19:0] field and a 2-bit ADDRESS[1:0]

field as shown below. The address field is used to decode the internal register address. Data is clocked into the shift register in

the direction from MSB to LSB, when the CLOCK signal goes high. On the rising edge of Load Enable (LE) signal, data stored

in the shift register is loaded into the addressed latch.

MSB

LSB

DATA[19:0]

ADDRESS[1:0]

21

2

1

0

2.1.1 Registers’ Address Map

When Load Enable (LE) is transitioned high, data is transferred from the 22-bit shift register into the appropriate latch depending

on the state of the ADDRESS[1:0] bits. A multiplexing circuit decodes these address bits and writes the data field to the corre-

sponding internal register.

ADDRESS[1:0]

REGISTER

FIELD

ADDRESSED

0

0

Aux_R Register

0

1

Aux_N Register

1

0

Main_R Register

1

1

Main_N Register

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