YMF721 datasheet(22/41 Pages) LSI

22 / 41 page

YMF721

July 10, 1997

- 22 -

7-4. Others

Power Supply

It is recommended to install a line noise filter in the YMF721 (OPL4-ML2). Be sure to install 0.1uF

ceramic capacitor between each of VDD pins and VSS pins as close to the pins as possible, especially

the pin No. 63 (VDD).

5V/3V

When operating YMF721 (OPL4-ML2) with 5 V, 5V/3V pin must be pulled up. When operating it

with 3.3 V, set the pin to "L".

XI, XO

YMF721 (OPL4-ML2) requires the clock frequency of 33.8688 MHz. This signal can be supplied

from the system or from the self-oscillation circuit connected with crystal oscillator

Yamaha recommends either of the following two types of parallel resonance type oscillator

made by Daishinku Co., Ltd.

(i) 3rd Overtone Type

AT-49, SMD-49 : R=5.6K, c1=c2=10pF

(ii) Fundamental Type

AT-49, SMD-49 : R=1M, c1=c2=5pF

Use of the Crystal oscillator with frequency deviation within 100 ppm is recommended. Length of

wiring lead from XI and XO pin to each component (crystal, resistor and capacitor) should be 0.5

inch or less respectively and the circuit pattern should be shielded on its periphery to minimize effect

on the peripheral devices.

Since YMF721 (OPL4-ML2) is able to use power down mode, the power consumption can be

minimized when generation of the clock signal is discontinued during this mode.

YMF721(OPL4-ML2)

100

33.8688MHz

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