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LP3961 데이터시트(PDF) 2 Page - National Semiconductor (TI) |
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LP3961 데이터시트(HTML) 2 Page - National Semiconductor (TI) |
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2 / 20 page ![]() Typical Application Circuits (Continued) Block Diagram LP3961 DS101129-2 # Minimum output capacitance is 10 µF to ensure stability over full load current range. More capacitance provides superior dynamic performance and additional sta- bility margin. *SD and ERROR pins must be pulled high through a 10k Ω pull-up resistor. Connect the ERROR pin to ground if this function is not used. See applications section for more information. DS101129-3 www.national.com 2 |
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