SSD1828Z datasheet(39/43 Pages) ETC

39 / 43 page

SSD1828

Rev 1.10

07/2002

SOLOMON

Table 17 - Parallel Timing Characteristics (TA = -40 to 85

°C, VDD = 2.7V, VSS =0V)

Symbol

Parameter

Min

Typ

Max

Unit

tcycle

Clock Cycle Time (write cycle)

100

500

tAS

Address Setup Time

tAH

Address Hold Time

tDSW

Write Data Setup Time

tDHW

Write Data Hold Time

tDHR

Read Data Hold Time

tOH

Output Disable Time

tACC

Access Time (RAM)

Access Time (command)

PWCSL

Chip Select Low Pulse Width (read RAM)

Chip Select Low Pulse Width (read Command)

Chip Select Low Pulse Width (write)

250

PWCSH

Chip Select High Pulse Width (read)

Chip Select High Pulse Width (write)

100

Rise Time

Fall Time

Valid Data

cycle

DSW

DHR

AC C

D/C

0-D7

RD (E)

Valid Data

0-D7

(Write data to driver)

(Read data from driver)

DH W

CSL

CSH

WR (R/W)

Figure 13 - Parallel 8080-series Interface Timing Characteristics (PS0 = H, PS1 = L)

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