| 전자부품 데이터시트 검색엔진 |
|
STR710FZ2T6 데이터시트(PDF) 36 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
STR710FZ2T6 데이터시트(HTML) 36 Page - STMicroelectronics |
|
36 / 49 page ![]() STR71xF - ELECTRICAL CHARACTERISTICS 36/49 Table 18. PLL2 Electrical Characteristics fFREE1 PLL free running frequency FREF_RANGE = 0 MX[1:0]=’01’ or ‘11’ 1MHz FREF_RANGE = 0 MX[1:0]=’00’ or ‘10’ 2MHz FREF_RANGE = 1 MX[1:0]=’01’ or ‘11’ 2MHz FREF_RANGE = 1 MX[1:0]=’00’ or ‘10’ 4MHz tLOCK1 PLL lock time FREF_RANGE = 0 Stable Input Clock Stable V33IOPLL, V18 300 µs FREF_RANGE = 1 Stable Input Clock Stable V33IOPLL, V18 600 µs ∆tJITTER1 PLL jitter (peak to peak) tPLL = 4 MHz, MX[1:0]=’11’ Global Output division = 32 (Output Clock = 2 MHz) 0.7 2 ns Symbol Parameter Test Conditions Value Unit Min Typ Max fPLLCLK2 PLL output clock fPLL x 28 140 MHz fPLL2 PLL input clock FREF_RANGE = 0 1.5 3.0 MHz FREF_RANGE = 1 3.0 5 MHz tLOCK2 PLL lock time FREF_RANGE = 0 Stable Input Clock Stable V33IOPLL, V18 300 µs FREF_RANGE = 1 Stable Input Clock Stable V33IOPLL, V18 600 µs ∆tJITTER2 PLL jitter (peak to peak) tPLL = 4 MHz, MX[1:0]=’11’ Global Output division = 32 (Output Clock = 2 MHz) 0.7 2 ns Symbol Parameter Test Conditions Value Unit Min Typ Max |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |