TMS320VC5501 datasheet(79/193 Pages) TI

79 / 193 page

Functional Overview

December 2002 − Revised November 2004

SPRS206H

3.10.2.6 IDLE3 Mode

In IDLE3 mode, all modules (including the CLOCK module) are set to idle state. To place the 5501 in IDLE3

mode, perform the following steps:

Clear (i.e., set to ‘0’) the PLLEN bit in PLLCSR to place the PLL in bypass mode.

Set the PLLPWRDN and PLLRST bits in PLLCSR to ‘1’.

Write a ‘1’ to all peripheral module bits in PICR (write 0x3FFF to PICR).

Write a ‘1’ to the HPI and DMA bits in MICR (write 0x0003 to MICR).

Write a ‘1’ to all domain bits and bit 9 in the ICR (write 0x03FF to ICR).

Execute the IDLE instruction.

PLL core is set to power-down mode and all internal clocks are disabled.

3.10.2.7 IDLE3 Mode With Internal Oscillator Disabled

In this state, all modules (including the CLOCK module) are set to the idle state and the internal oscillator is

set to the power-down mode. This is the lowest power-consuming state that 5501 can be placed under.

Clear (i.e., set to ‘0’) the PLLEN bit in PLLCSR to place the PLL in bypass mode.

Set the PLLPWRDN, PLLRST, and OSCPWRDN bits in PLLCSR to ‘1’.

Set the WKEN register to specify which event will wake up internal oscillator [e.g., set bit 1 to have

interrupt 0 (INT0) wake up the oscillator].†

Write a ‘1’ to all peripheral module bits in PICR (write 0x3FFF to PICR).

Write a ‘1’ to the HPI and DMA bits in MICR (write 0x0003 to MICR).

Write a ‘1’ to all domain bits and bit 9 in the ICR (write 0x03FF to ICR).

Execute the IDLE instruction.

Internal oscillator is set to power-down mode, PLL core is set to power-down mode, and all internal clocks

are disabled.

Note that the internal oscillator can be awakened through an NMI or external interrupt as long as that event

is specified in the Oscillator Wakeup Control Register and, in the case of an external interrupt, the interrupt

is enabled in the CPU’s Interrupt Enable Register.

† Maskable external interrupts must be enabled through IER prior to setting the 5501 to IDLE.

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