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TMS55166 데이터시트(PDF) 28 Page - Texas Instruments

부품명 TMS55166
상세설명  262144 BY 16-BIT MULTIPORT VIDEO RAM
PDF  70 Pages
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제조업체  TI [Texas Instruments]
홈페이지  http://www.ti.com
Logo TI - Texas Instruments

TMS55166 데이터시트(HTML) 28 Page - Texas Instruments

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TMS55165, TMS55166, TMS55175, TMS55176
262144 BY 16-BIT MULTIPORT VIDEO RAM
SMVS463 – DECEMBER 1995
28
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
split-register-transfer read
In split-register-transfer operations, the serial-data register is split into halves. The low half contains bits 0 – 127,
and the high half contains bits 128 – 255 (see Figure 20). While one half is being read out of the SAM port, the
other half can be loaded from the memory array.
512
× 512
Memory Array
256 - Bit
Data Register
0
255 256
511
0
255
A8 = 0
A8 = 1
Figure 20. Split-Register-Transfer Read
To invoke a split-register-transfer cycle, DSF is brought high, TRG is brought low, and both are latched at the
falling edge of RAS (see Figure 21). Nine row-address bits (A0 – A8) are also latched at the falling edge of RAS
to select one of the 512 rows available for the transfer. Eight of the nine column-address bits (A0 – A6 and A8)
are latched at the falling edge of CAS. Column-address bit A8 selects which half of the row is to be transferred.
Column-address bit A7 is ignored, and the split-register transfer is internally controlled to select the inactive half.
Column-address bits A0 – A6 select one of 127 tap points in the specified half of SAM. Locations 127 and 255
are not valid tap points in split-register-transfer operations. In stop-point mode, stop-point locations are not valid
tap points in split-register-transfer operations.
Full XFER
RAS
Split XFER
Split XFER
Split XFER
AB
0511
A8 = 0
AB
0
255
SQ
AB
C
0
A7 = 0† 511
A8 = 1
CB
0
255
AB
C
D
0
A7 = 1† 511
A8 = 1
CD
0
255
SQ
AB
C
D
E
0 A7 = 0†
511
A8 = 0
ED
0
255
SQ
SQ
DRAM
SAM
† A7 shown is internally controlled.
Figure 21. Example of a Split-Register-Transfer Read Operation
A full-register transfer must precede the first split-register transfer to ensure proper operation. After the
full-register transfer cycle, the first split-register transfer can follow immediately without any minimum SC clock
requirement (see Figure 22).



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