FT4232HL datasheet(21/55 Pages) FTDI

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FT4232H QUAD HIGH SPEED USB TO MULTIPURPOSE UART/MPSSE IC

Datasheet

Version 2.4

Document No.: FT_000060 Clearance No.: FTDI#78

Dual Port FIFO RX Buffer (2Kbytes per channel). Data from the Multi-purpose UART/FIFO controllers

is stored in these blocks to be sent back to the Host PC when requested. This is controlled by the USB

Protocol Engine and FIFO control block.

RESET Generator - The integrated Reset Generator Cell provides a reliable power-on reset to the device

internal circuitry at power up. The RESET# input pin allows an external device to reset the FT4232H.

RESET# should be tied to VCCIO (+3.3v) if not being used.

Independent Baud Rate Generators - The Baud Rate Generators provides an x16 or an x10 clock input

to the UART’s from a 120MHz reference clock and consists of a 14 bit pre-scaler and 4 register bits which

provide fine tuning of the baud rate (used to divide by a number plus a fraction). This determines the Baud

Rate of the UART which is programmable from 183 baud to 12 million baud. The FT2232H does not support

the baud rates of 7 Mbaud 9 Mbaud, 10 Mbaud and 11 Mbaud.

See FTDI application note AN232B-05 on the FTDI website (www.ftdichip.com) for more details.

+1.8V LDO Regulator. The +1.8V LDO regulator generates the +1.8 volts for the core and the USB

transceiver cell. Its input (VREGIN) must be connected to a +3.3V external power source. It is also

recommended to add an external filtering capacitor to the VREGIN. There is no direct connection from the

+1.8V output (VREGOUT) and the internal functions of the FT4232H. The PCB must be routed to connect

VREGOUT to the pins that require the +1.8V including VREGIN.

UTMI PHY. The Universal Transceiver Macrocell Interface (UTMI) physical interface cell. This block handles

the Full speed / High Speed SERDES (serialise – de-serialise) function for the USB TX/RX data. It also

provides the clocks for the rest of the chip. A 12 MHz crystal should be connected to the OSCI and OSCO

pins. A 12K Ohm resistor should be connected between REF and GND on the PCB.

The UTMI PHY functions include:



Supports 480 Mbit/s "High Speed" (HS)/ 12 Mbit/s “Full Speed” (FS), FS Only and "Low Speed"

(LS).



SYNC/EOP generation and checking.



Data and clock recovery from serial stream on the USB.



Bit-stuffing/unstuffing; bit stuff error detection.



Manages USB Resume, Wake Up and Suspend functions.



Single parallel data clock output with on-chip PLL to generate higher speed serial data clocks.

EEPROM Interface. When used without an external EEPROM the FT4232H defaults to a quad USB to an

asynchronous serial port device. Adding an external 93C46 (93C56 or 93C66) EEPROM allows

customization of USB VID, PID, Serial Number, Product Description Strings and Power Descriptor value of

the FT4232H for OEM applications. Other parameters controlled by the EEPROM include Remote Wake Up,

Soft Pull Down on Power-Off and I/O pin drive strength.

The EEPROM must be a 16 bit wide configuration such as a Microchip 93LC46B or equivalent capable of a

1Mbit/s clock rate at VCC = +3.00V to 3.6V. The EEPROM is programmable in-circuit over USB using a

utility program called FT_PROG available from FTDI’s web site (www.ftdichip.com). This allows a blank

part to be soldered onto the PCB and programmed as part of the manufacturing and test process.

If no EEPROM is connected (or the EEPROM is blank), the FT4232H will default to serial ports. The device

uses its built-in default VID (0403), PID (6011) Product Description and Power Descriptor Value. In this

case, the device will not have a serial number as part of the USB descriptor.

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