IOBUS1 datasheet(59/88 Pages) FTDI

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Datasheet

Vinculum-II Embedded Dual USB Host Controller IC

V ers ion 1 .7

Doc ument N o.: FT _000138 C learance N o.: FT DI# 1 43

64 Pin

Package

Available

pins

48 Pin

Package

Available

pins

32 Pin

Package

Available

pins

Name

Type

Description

12, 16,

20, 25,

29, 40,

44, 48,

52, 58,

12,16,

21, 32,

36, 42,

12, 24,

fifo_txe#

Output

When high, do not write data into the FIFO.

When low, data can be written into the FIFO

by strobing fifo_wr# high, then low.

13, 17,

22, 26,

31, 41,

45, 49,

55, 59,

13, 18,

22, 33,

37, 43,

14, 25,

fifo_rd#

Input

Enables the current FIFO data byte on

D0...D7 when low. Fetches the next FIFO

data byte (if available) from the receive

FIFO buffer when fifo_rd# goes from high to

low

14, 18,

23, 27,

32, 42,

46, 50,

56, 60,

14, 19,

23, 34,

38, 44,

15, 26,

fifo_wr#

Input

Writes the data byte on the D0...D7 pins

into the transmit FIFO buffer when fifo_wr#

goes from high to low.

Table 6.16 Data and Control Bus Signal Mode Options - Parallel FIFO Interface

6.6.2 Read / Write Transaction Asynchronous FIFO Mode

When in Asynchronous FIFO interface mode, the timing of read and write operations on the FIFO

interface are shown in Figure 6.22 and Table 6.17.

In asynchronous mode an external device can control data transfer driving FIFO_WR# and FIFO_RD#

inputs. In contrast to synchronous mode, in asynchronous mode the 245 FIFO module generates the

output enable EN# signal. EN# signal is effectively the read signal RD#.

Current byte is available to be read when FIFO_RD# goes low. When FIFO_RD# goes high, FIFO_RXF#

output will also go high. It will only become low again when there is another byte to read.

When FIFO_WR# goes low FIFO_TXE# flag will always go high. FIFO_TXE# goes low again only when

there is still space for data to be written in to the module.

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