AD7725 datasheet(2/28 Pages) AD

2 / 28 page

REV. A

–2–

AD7725–SPECIFICATIONS1(AVDD = 5 V 5%, AGND = AGND1 = AGND2 = DGND= 0 V,

fCLKIN

2 = 9.6 MHz, REF2 = 2.5 V, T

A = TMIN to TMAX, unless otherwise noted.)

B Version

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

DYNAMIC SPECIFICATIONS

When tested with the FIR filter in

Figure 1, HALF_PWR = Logic High

Bipolar Mode

Signal-to-Noise

Measurement Bandwidth = 0.5

2.5 V Reference

3 V Reference

Total Harmonic Distortion

3, 5

–94

–86

Spurious Free Dynamic Range

3, 5

–98

–89

Unipolar Mode

Signal-to-Noise

Measurement Bandwidth = 0.5

Total Harmonic Distortion

3, 5

–94

ANALOG INPUTS

Full-Scale Input Span

VIN(+) – VIN(–)

Bipolar Mode

Differential or Single-Ended Input

±4/5

VREF2

Unipolar Mode

Single-Ended Input

8/5

VREF2

Absolute Input Voltage

VIN(+) and/or VIN(–)

AGND

AVDD

Input Sampling Capacitance

Input Sampling Rate, fCLKIN

14.4

MHz

CLOCK

CLKIN Duty Ratio

REFERENCE

REF1 Output Resistance

3.5

Ω

Reference Buffer

Offset Voltage

Offset between REF1 and REF2

±3mV

Using Internal Reference

REF2 Output Voltage

2.39

2.54

2.69

REF2 Output Voltage Drift

ppm/

°C

Using External Reference

REF2 Input Impedance

REF1 = AGND

Ω

REF2 External Voltage Input

2.5

STATIC PERFORMANCE

Resolution

Bits

Differential Nonlinearity (DNL)

Guaranteed Monotonic

±0.5

±18

LSB

Integral Nonlinearity (INL)

±2

LSB

DC CMRR

Offset Error

±20

Gain Error

3, 9

±0.5

%FSR

LOGIC INPUTS (Excluding CLKIN)

VINH, Input High Voltage

2.0

VINL, Input Low Voltage

0.8

CLOCK INPUT (CLKIN)

VINH, Input High Voltage

0.7

DVDD

VINL, Input Low Voltage

0.3

DVDD

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