전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

CS8904 데이터시트(PDF) 13 Page - Cirrus Logic

부품명 CS8904
상세설명  ETHERNET TRANSCEIVER
PDF  34 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  CIRRUS [Cirrus Logic]
홈페이지  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS8904 데이터시트(HTML) 13 Page - Cirrus Logic

Back Button CS8904 Datasheet HTML 9Page - Cirrus Logic CS8904 Datasheet HTML 10Page - Cirrus Logic CS8904 Datasheet HTML 11Page - Cirrus Logic CS8904 Datasheet HTML 12Page - Cirrus Logic CS8904 Datasheet HTML 13Page - Cirrus Logic CS8904 Datasheet HTML 14Page - Cirrus Logic CS8904 Datasheet HTML 15Page - Cirrus Logic CS8904 Datasheet HTML 16Page - Cirrus Logic CS8904 Datasheet HTML 17Page - Cirrus Logic Next Button
Zoom Inzoom in Zoom Outzoom out
 13 / 34 page
background image
DS191PP2
13
CS8904
Crystal LAN™ Quad Ethernet Transceiver
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
3.2.1 Encoder
The encoder converts NRZ data from the digital
controller and a 10 MHz Transmit Clock signal into
a serial stream of Manchester data. The Transmit
Clock is produced by an on-chip oscillator circuit
that is driven by either an external 20 MHz quartz
crystal or a TTL-level CMOS clock input. The
encoded signal is routed to the 10BASE-T
transceiver.
3.2.2 Carrier Detection
The internal Carrier Detection circuit informs the
digital controller that valid receive data is present
by asserting the Carrier Detect (CD) signal as soon
it detects a valid Ethernet preamble. During normal
packet reception, Carrier Detect remains asserted
while the frame is being received, and is de-
asserted after the last low-to-high transition of the
End-of-Frame (EOF) sequence. Whenever the
receiver is idle (no receive activity), Carrier Detect
remains de-asserted.
3.2.3 Clock and Data Recovery
When the receiver is idle, the phase-lock loop
(PLL) is locked to the internal clock signal. The
assertion of the Carrier Sense signal interrupts the
PLL. When it restarts, it locks on the incoming
data. The receive clock is then compared to the
incoming data at the bit cell center and any phase
difference is corrected. The PLL remains locked as
long as the receiver input signal is valid. Once the
PLL has locked on the incoming data, the ENDEC
converts the Manchester data to NRZ and passes
the decoded data and the recovered clock to the
digital controller for further processing.
3.3 10BASE-T Transceiver
The
CS8904
includes
integral
10BASE-T
transceivers that are compliant with the relevant
portions of clause 14 of the Ethernet standard
(ISO/IEC 8802-3:1996). It includes all analog and
digital circuitry needed to interface the CS8904
directly to a simple isolation transformer (see
Figure 2 for a connection diagram). Figure 5
provides a block diagram of one of the 10BASE-T
transceivers.
RX
TX
Auto-Negotiation
and Link Pulse
TX Pre-
Distortion
TX Filters
Filter Tuning
RX Filters
TX Drivers
Rx+
Rx-
Tx+
Tx-
ENDEC
Auto-Negotiation and Link
Control and Status
10BASE-T Transceiver
RX
Comparator
Figure 5. 10BASE-T Transceiver



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34


데이터시트 다운로드

Go To PDF Page


링크 URL



ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크 투 데이터시트    |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com