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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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ST25R3910 데이터시트(PDF) 21 Page - STMicroelectronics |
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ST25R3910 데이터시트(HTML) 21 Page - STMicroelectronics |
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21 / 65 page  DocID029768 Rev 2 21/65 ST25R3910 Functional overview 35 Figure 8. SPI communication: loading of FIFO Reading received data from FIFO Reading received data from the FIFO is similar to reading data from an addressable registers. Difference is that in case of reading more bytes they all come from the FIFO. SPI operation mode bits 10 indicate FIFO operations. In case of reading the received data from the FIFO all bits <C5 – C0> are set to 1. On the following SCLK rising edges the data from FIFO appears as in case of read data from addressable registers. If the command is terminated by putting SEN low before a packet of 8 bits (one byte) is read, that particular byte is considered unread and will be the first one read in next FIFO read operation. Figure 9. SPI communication: reading of FIFO |
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