pull-down resistors are not required. Due to the nature of the

output stage, both its on and off impedance values vary as a

function of the display voltage applied. However,

Figures 3, 4

show that this output impedance will remain constant for a

fixed value of display voltage.

Figure 5 demonstrates the critical timing requirements be-

tween CLOCK and DATA IN for the MM58342.

To clear (reset) the display driver at power on or any time,

the following flushing routine may be used. With the enable

signal high, clock in 20 zeroes. Drive the enable signal low

and the display will be blank. It is recommended to clear the

driver at power on.

In

Figure 6, the ENABLE signal acts as an envelope, and

only while this signal is at a logic “1” does the circuit accept

CLOCK input signals. Data is transferred and shifted in the

internal shift register on the rising clock edge, i.e., “0”–“1”

transition. When the ENABLE signal goes low, the contents

of the shift registers are latched, and the display will show

new data. During data transfer, the display will show old

data. DATA OUT is also provided on the MM58342 being

output on the falling edge. At any time, the display may be

blanked under processor control, using the BLANKING

CONTROL input.

Figure

7

shows

a

schematic

diagram

of

a

microprocessor-based system where the MM58342 is used

to provide the grid drive for a 40-digit 2 line5x7 multiplexed

vacuum fluorescent (VF) display. The anode drive in this

example is provided by another member of the high voltage

display driver family, namely the MM58348, which does not

require an extremely generated load signal.

Timing Diagrams

00792503

FIGURE 3. Output Impedance Off

00792504

FIGURE 4. Output Impedance On

00792505

FIGURE 5. Clock and Data Timings

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