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LP2994MX 데이터시트(PDF) 14 Page - National Semiconductor (TI) |
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LP2994MX 데이터시트(HTML) 14 Page - National Semiconductor (TI) |
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14 / 15 page ![]() Typical Application Circuits (Continued) with the DDR-SDRAM DIMMs mounted on modules. As a result bulk aluminum electrolytic capacitors in the range of 1000uF are typically used. PCB Layout Considerations 1. The input capacitor for the power rail should be placed as close as possible to the PVIN pin. 2. V SENSE should be connected to the VTT termination bus at the point where regulation is required. For mother- board applications an ideal location would be at the center of the termination bus. 3. V DDQ can be connected remotely to the VDDQ rail input at either the DIMM or the Chipset. This provides the most accurate point for creating the reference voltage. 4. For improved thermal performance excessive top side copper should be used to dissipate heat from the pack- age. Numerous vias from the ground connection to the internal ground plane will help. Additionally these can be located underneath the package if manufacturing stan- dards permit. 5. Care should be taken when routing the V SENSE trace to avoid noise pickup from switching I/O signals. A 0.1uF ceramic capacitor located close to the V SENSE can also be used to filter any unwanted high frequency signal. This can be an issue especially if long V SENSE traces are used. www.national.com 14 |
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