Mechanical and electrical characteristics

L2G2IS

12/26

DocID027248 Rev 2

3.4

SPI - serial peripheral interface

Subject to general operating conditions for Vdd and Top.

Figure 3. SPI slave timing diagram

Note:

Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both input and output

ports.

Table 6. SPI slave timing values

Symbol

Parameter

Unit

Min

Max

SPI clock cycle

100

ns

SPI clock frequency

10

MHz

CS setup time

5

ns

CS hold time

8

SDI input setup time

5

SDI input hold time

15

SDO valid output time

50

SDO output hold time

6

SDO output disable time

50

1. Values are guaranteed at 10 MHz clock frequency for SPI, based on characterization results, not tested in production.