MPC8240 datasheet(12/52 Pages) MOTOROLA

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MPC8240 Integrated Processor Hardware Specifications

MOTOROLA

Electrical and Thermal Characteristics

clock frequency and the settings of the PLL_CFG[0:4] signals. Parts are sold by maximum processor core

frequency; see Section 1.9, “Ordering Information,” for information on ordering parts.

1.4.2.1

AC Operating Frequency Data

Table 6 provides the operating frequency information for the MPC8240.

1.4.2.2

Clock AC Specifications

Table 7 provides the clock AC timing specifications as defined in Section 1.4.2.3, “Input AC Timing

Specifications.”

Table 6. Operating Frequency

At recommended operating conditions (see Table 2) with GVDD = 3.3 V ± 5% and LVDD = 3.3 V ± 5%

Characteristic 1

200 MHz

250 MHz 2

Unit

Min

Max

Min

Max

Processor frequency (CPU)

100

200

100

250

MHz

Memory bus frequency

33–100

MHz

PCI input frequency

25–66

MHz

Note:

1. Caution: The PCI_SYNC_IN frequency and PLL_CFG[0:4] settings must be chosen such that the resulting

peripheral logic/memory bus frequency and CPU (core) frequency do not exceed their respective maximum or

minimum operating frequencies. Refer to the PLL_CFG[0:4] signal description in Section 1.6, “PLL Configurations,”

for valid PLL_CFG[0:4] settings and PCI_SYNC_IN frequencies.

2.) The 250-MHz processor is only available as an R spec part. See Section 1.9.2, “Part Numbers Not Fully Addressed

by This Document,” for more information.

Table 7. Clock AC Timing Specifications

At recommended operating conditions (see Table 2) with LVDD = 3.3 V ± 0.3 V

Num

Characteristic and Condition 1

Min

Max

Unit

Notes

Frequency of operation (PCI_SYNC_IN)

MHz

PCI_SYNC_IN cycle time

2, 3

PCI_SYNC_IN rise and fall times

—

2.0

PCI_SYNC_IN duty cycle measured at 1.4 V

PCI_SYNC_IN pulse width high measured at 1.4 V

PCI_SYNC_IN pulse width low measured at 1.4 V

PCI_SYNC_IN jitter

—

150

PCI_CLK[0:4] skew (pin-to-pin)

—

500

SDRAM_CLK[0:3] skew (pin-to-pin)

—

350

Internal PLL relock time

—

100

µs

3, 4, 6

DLL lock range with DLL_STANDARD = 1

≤ (NT

clk – tloop – tfix0) ≤ 7ns

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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