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NSC800N 데이터시트(PDF) 17 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
부품명 NSC800N
상세설명  NSC800TM High-Performance Low-Power CMOS Microprocessor
PDF  76 Pages
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제조업체  NSC [National Semiconductor (TI)]
홈페이지  http://www.national.com
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NSC800N 데이터시트(HTML) 17 Page - National Semiconductor (TI)

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90 Timing and Control (Continued)
During the opcode fetch the CPU places the contents of
the PC on the address bus The falling edge of ALE indi-
cates a valid address on the AD(0 – 7) lines The WAIT input
is sampled during t2 and if active causes the NSC800 to
insert a wait state (tw) WAIT is sampled again during tw so
that when it goes inactive the CPU continues its opcode
fetch by latching in the data on the rising edge of RD from
the AD(0 – 7) lines During t3 RFSH goes active and AD(0–
7) has the dynamic RAM refresh address from register R
and A(8 – 15) the interrupt vector from register I
TLC5171 – 17
FIGURE 10a Memory ReadWrite Cycles without WAIT States
TLC5171 – 18
FIGURE 10b Memory Read and Write with WAIT States
17



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