STS1TX datasheet(48/70 Pages) STMICROELECTRONICS

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MCU interface

STS1TX

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DocID025109 Rev 1

MCU interface

Communication with the MCU goes through a standard 4-wire SPI interface and 4 GPIOs.

The device is able to provide a system clock signal to the MCU.

MCU performs the following operations:

•

Program the STS1TX in different operating modes by sending commands

•

Read and write buffered data, and status information from the SPI

•

Get interrupt requests from the GPIO pins

•

Apply external signals to the GPIO pins

10.1

Serial peripheral interface

The STS1TX is configured by a 4-wire SPI-compatible interface (CSn, SCLK, MOSI, and

MISO). More specifically:

•

CSn: chip select, active low

•

SCLK: bit clock

•

MOSI: data from MCU to STS1TX (STS1TX is the slave)

•

MISO: data from STS1TX to MCU (MCU is the master).

As the MCU is the master, it always drives the CSn and SCLK. According to the active

SCLK polarity and phase, the STS1TX SPI can be classified as mode 1 (CPOL=0,

CPHA=0), which means that the base value of SCLK is zero, data are read on the clock’s

rising edge and data are changed on the clock's falling edge. The MISO is in tri-state mode

when CSn is high. All transfers are done most significant bit first.

The SPI can be used to perform the following operations:

•

Write data (to registers or FIFO queue)

•

Read data (from registers or FIFO queue)

•

Write commands.

The SPI communication is supported in all the active states, and also during the low power

state: STANDBY and SLEEP (see Table 18: States).

When accessing the SPI interface, the two status bytes of the MC_STATE[1:0] registers are

sent to the MISO pin. The timing diagrams of the three operations above are reported

below.

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